0.6um 1P2MCMOS process platform。0.6um gate length,single poly, double metal, application for Power management product,Core/IO voltage:5.0V, (24V optional)。FMIC has the elaborate design rule document.
Process features
Ø Single poly, double metal, twin well.
Ø Core/IO voltage:5.0V, Vds>5V, Vgs>5V. (24V optional)
Ø Substrate silicon material is p-type <100>, 15-25ohm-cm.
Ø 11 masks and 13 photo layers.
Ø N-Type mask Rom code for option.
Ø Standard LOCOS process for isolation.
Ø 150A gate oxide, poly for gate electrode.
Ø NLDD, PLDD and spacer structure.
Ø Ti/TiN/AlSiCu/TiN stack layer for interconnection.
Ø Oxide and nitride stack layer for passivation.
Ø IMD planarization process.
Applications
Ø DC-DC Converter
Ø Power management product
Ø Battery protection IC
Ø LED Driver